1. Field of the Invention
The present invention relates generally to detecting defects in circuit boards or integrated circuit chip carriers.
2. Problem to be Solved
Circuit boards and integrated circuit (IC) chip carriers, such as single chip module (SCM), multi-chip module (MCM) and hybrid chip carriers are typically used for mounting and interconnecting electronic components in most electronic equipment. Such circuit boards or IC chip carriers usually include metal interconnections, voltage planes, a ground plane and dielectric materials such as ceramic, glass ceramic, silicon-oxide, polymer and/or epoxy glass. The circuit boards also include a plurality of interconnection networks ("nets"). Each net may be distributed either across a single layer or across multiple layers within the circuit board.
As packaging density in such boards continues to increase, the metal interconnections which comprise each interconnection network are decreasing in size and are being spaced closer together. Such continual miniaturization of the metal interconnections within the circuit boards or chip carriers results in an increase in the probability of a variety of defects. For example, the points of a conductor network that should be connected together may have one (or more) discontinuities in the conductor path(s). This results in an "open circuit" condition having substantially infinite resistance between certain sections of the network. A further defect occurs when two independent conductor networks or conductor areas that are supposed to have no electrical connection and therefore substantially infinite internet resistance, in fact display an unacceptable, low value of internet resistance. This is commonly referred to as a "short circuit". In addition, a conductive pathway may be defective because it displays one or more sections having resistances which exceed an acceptable level. This defect is referred to as a "resistive fault". In a properly manufactured high-density passive board, the resistance between terminals of a common conductor network is normally in the range of from a few milliohms to many ohms. This resistance is dependent on the length and cross-section of the conductors. Furthermore, the resistance between independent networks should approach infinity. This resistance typically exceeds 100 megohms.
A necessary step in the manufacture of high-density substrates, chip carriers, and passive boards is to test the proper continuity and isolation of all nets before any electronic components are mounted. Continuity testing measures relatively low resistance within particular networks. Open circuits and resistive faults are thus typical defects which are found in continuity testing. Isolation testing measures the expected high resistance levels that should exist between conductors. Short circuits are typical defects which are found when conducting isolation testing.
A common continuity and isolation test method uses cluster probes which match and contact test pads on the substrate surface. By controlling the switching matrix, resistance from a network under test to all other networks in the substrate can be measured. This is a relatively fast testing method, however, it lacks flexibility. Substrates with different designs usually require different cluster probes or "bed-of-nail" fixtures. In addition, complexity and long lead-time to produce custom cluster probes make this technique costly especially for early manufacturing where product design may not be finalized.
Another isolation test is the so called point-to-point or single probe testing wherein two moving probes are used on an X-Y positioning mechanism. This flexible probing method can perform individual tests between all possible pairs of nets. In this method, testing of passive substrates is accomplished by using moving probes in a series of two-point resistance measurements. In this manner, the continuity of individual nets may be verified. This method allows a series of one-point measurements to be made to determine the capacitance of a network relative to a reference plane or indicate short-circuits between nets through excessive internet capacitance. While this approach has great flexibility, it suffers from several severe practical difficulties which limit its effectiveness and speed. These include a need for switching between resistance and capacitive test modes, lengthy cycle times, difficulty of detecting a low-capacitance net shorted to a high-capacitance net when testing the high capacitance net, and an inability to distinguish between a high-resistance short to a net and a leakage path directly to ground. Furthermore, this method relies on simple scalar matching of capacitance values during the defect isolation process. In this manner, the continuity of nets which display excessive capacitance is checked against a potentially long list of other nets showing similar capacitance.
Bearing in mind the problems and deficiencies of conventional processes and systems for testing circuit boards, it is an object of the present invention to provide a new and improved system for testing the integrity of circuit boards.
It is another object of the present invention to provide a new and improved system for identifying defects in circuit boards that requires relatively fewer components than conventional testing systems.
It is a further object of the present invention to provide a new and improved system for testing the integrity of interconnection networks on circuit boards or unpopulated chip carriers in relatively less time than conventional testing systems.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.